The electronics industry, as we see today, includes a wide verity of devices which use signal processing in one form or another. Starting from loud speakers, mobile phones to radio transceivers, almost every electronic device involves signal processing. Many of such electronic devices involve conversion of analog signals into digital signals and others involve vice versa. Generally speaking, digital signals are preferred in the electronics industry over the analog signals since a digital signal has a higher margin for error i.e. a digital signal is less error prone. Additionally, a digital signal is well defined and orderly and therefore, it is easier to distinguish from background noise resulting in high quality output from signal processing.
An analog signal may be converted into a digital signal using a process of analog to digital conversion and a device which performs such conversion is called an Analog to Digital Converter (ADC). An ADC converts an analog signal into digital equivalent without altering the information contained in the analog signal. A number of ADCs are available today, among these ADCs a special class of ADC is Pulse Width Modulation Analog to Digital Converter (PWM ADC). A PWM ADC uses Pulse Width Modulation (PWM) techniques for converting an analog signal into a digital signal.
For converting an analog signal into a digital signal, a PWM ADC samples the analog signal at various time instances and obtains a plurality of sample values corresponding to each time instance. The rate of obtaining sample values, i.e. the sample rate, is determined by a decimation clock (RCLK) of the PWM ADC. Thereafter, the sample values are quantized by a quantizer by mapping the sample values to one of a set of discrete quantization levels. The number of quantization levels is determined by a Quantizer clock (QCLK) of the PWM ADC.
It will be apparent that the more the number of quantization levels used, the better the resolution of the digital signal produced. Therefore, the QCLK is kept very high as compared to the RCLK in a PWM ADC. Since the two clocks are separate in a conventional PWM ADC, it is possible to adjust a frequency for each of the RCLK and the QCLK. The two clocks are adjusted in such a way that the ratio of QCLK and RCLK is an integer.
After generation, the PWM signal is decimated using a decimator. Decimation is a process of reducing the number of sample values in a discrete time signal, for instance a PWM signal. A decimator generates a Pulse Code Modulated (PCM) signal starting from a PWM signal as input. A typical PWM ADC system uses a Finite Impulse Response (FIR) based decimation techniques. Such techniques work well in cases where the QCLK and the RCLK are in an integer relation with each other, i.e., the ratio of QCLK and RCLK is an integer. However, the QCLK and the RCLK may not be in an integer relation with each other for all the cases.
Various cases in decimation of PWM signal may arise in which the relationships between the QCLK and the RCLK may be an integer or a non integer. As an example, a PWM ADC used in Radio transceiver may have a defined RCLK due to the standards specified for a frequency on which the Radio transceiver intends to operate. Further, if a RF oscillator like, Variable Frequency Oscillator (VFO), present in the Radio transceiver is used as the QCLK, the QCLK also becomes extremely defined. Therefore, in such case ratio of the QCLK and the RCLK may not be an integer. Also, in some of the signal processing systems one or more of the QCLK and the RCLK may vary instantaneously which may change the integer relation between QCLK and RCLK.
Some existing methods decimate a PWM signal using FIR based techniques when ratio of the QCLK and the RCLK is not an integer. However, such methods use multiple FIR based decimators for decimation which increases the complexity of system. Also, for implementing such methods, interpolations between multiple decimators may be required. The use of interpolation may result in a loss in accuracy of the PCM signal produced. Other existing methods use Infinite Impulse Response (IIR) techniques for decimation. However, IIR based methods perform decimation by running a decimator at very high sample rates. In the case of a PWM ADC system, a decimator implementing IIR based decimation runs at the QCLK rate. Running the decimator at the QCLK rate makes processing of the PWM signal inefficient since more circuit area and more power is required for processing the PWM signal at a high sample rate.
Therefore, there is a need for a method and system for decimating a PWM signal when the QCLK and the RCLK are not in an integer relationship. There is a further need of a method and system which allows IIR based decimation at a lower sample rate.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.